11, DIL (dualin-line) DIP nickname (see DIP).
European semiconductor manufacturers use this name more.
12, DIP (dualin-linepackage) dual in-line package.
One of the plug-in packages, the leads are led out from both sides of the package, and the package materials are plastic and ceramic. DIP is the most popular plug-in package, and its application range includes standard logic IC, memory LSI, and microcomputer circuit.
The center of the pin is 2.54mm and the number of pins is from 6 to 64. The package width is typically 15.2mm. Some packages with widths of 7.52 mm and 10.16 mm are called skinnyDIP and slimDIP (narrow body type DIP), respectively. However, in most cases, it is not differentiated and is simply referred to as DIP. In addition, ceramic DIP sealed with low melting glass is also known as cerdip (see cerdip).
13, DSO (dualsmallout-lint)
Double-sided pin small outline package. Another name for SOP (see SOP). Some semiconductor manufacturers use this name.
14, DICP (dualtapecarrierpackage)
Double-sided pin-loaded package. One of TCP (on-package). The leads are fabricated on the insulating tape and pulled out from both sides of the package. Due to the TAB (Automatic On-Load Soldering) technology, the package is very thin. It is commonly used in liquid crystal display driver LSIs, but most of them are fixed products. In addition, a 0.5 mm thick memory LSI booklet package is in the development stage. In Japan, DICP is named DTP according to the EIAJ (Japan Electromechanical Industry) standard.
15, DIP (dualtapecarrierpackage)
Ibid. The Japanese Electronic Machinery Industry Association standard for the name of DTCP.
16, FP (flatpackage)
Flat package. One of the surface mount packages. Another name for QFP or SOP (see QFP and SOP). Some semiconductor manufacturers use this name.
Reverse soldering chips. One of the bare chip packaging technologies is to form metal bumps in the electrode regions of the LSI chip, and then bond the metal bumps to the electrode regions on the printed substrate. The footprint of the package is substantially the same as the chip size. It is the smallest and thinnest of all packaging technologies.
However, if the thermal expansion coefficient of the substrate is different from that of the LSI chip, a reaction occurs at the joint, thereby affecting the reliability of the connection. Therefore, it is necessary to reinforce the LSI chip with a resin and use a substrate material having substantially the same thermal expansion coefficient. The SiS756 North Bridge is available in the latest Flip-chip package and fully supports the AMDAthlon64/FX central processor. Support PCI ExpressX16 interface, providing graphics card up to 8GB / s two-way transmission bandwidth. Supports the highest HyperTransportTechnology with a transmission bandwidth of up to 2000MT/sMHz.
18, FQFP (finepitchquadflatpackage)
The small pin center is from the QFP. Usually refers to QFP with pin center distance less than 0.65mm (see QFP). Some conductor manufacturers use this name. The package form of PQFP (PlasticQuadFlatPackage) PQFP is the most common. The chip pins are very small, the pins are very thin, and many large-scale or large integrated circuits are used in this package form, and the number of pins is generally more than 100. The 80286, 80386 and some 486 motherboard chips in Chips in this package must be soldered to the board using SMT technology (surface mount equipment). Chips mounted using SMT technology do not have to be punctured on the board. The soldering to the motherboard can be achieved by aligning the legs of the chip with the corresponding solder joints. Chips soldered in this way are difficult to disassemble without speci Al tools. SMT technology is also widely used in the field of chip soldering, and many advanced packaging technologies have required SMT soldering.
19. CPAC (globetoppadarraycarrier)
American Motorola's nickname for BGA.
20, CQFP military wafer ceramic lithography package (CeramicQuadFlat-packPackage)
The wafer on the right is a military chip package (CQFP), which is what the package did before it was placed in the crystal. This package is only available in military products and aerospace industrial wafers. There is a thick gold compartment next to the wafer slot (higher, not visible on the photo) to prevent radiation and other interference. Screw holes are provided on the periphery to secure the wafer to the motherboard. The most interesting is the gold-plated pins around, which greatly reduces the thickness of the chip package and provides excellent heat dissipation.