LED Package Technology Commonly Used In 40 Kinds Of Chips (Part 1)

- Apr 08, 2019-

LED packaging technology is mostly developed and evolved on the basis of discrete device packaging technology, but it has great speciality. In general, the die of the discrete device is sealed within the package, and the package functions primarily to protect the die and complete the electrical interconnection. The LED package completes the output electrical signal to protect the die from working properly. Now I will introduce 40 kinds of packaging technologies.


1, BGA package (ballgridarray)


One of the spherical contact display, surface mount packages. A spherical bump is formed on the back surface of the printed substrate in place of the lead, and the LSI chip is mounted on the front surface of the printed substrate, and then sealed by a molding resin or a potting method. Also known as a bump display carrier (PAC). The pin can exceed 200 and is a package for multi-pin LSI. The package body can also be made smaller than the QFP (four-sided pin flat package). For example, a 360-pin BGA with a 1.5mm center-to-center pitch is only 31mm square; a 304-pin QFP with a 0.5mm center-to-center distance is 40mm square.


And BGA doesn't have to worry about pin deformation like QFP. The package was developed by Motorola Inc. of the United States, and was first adopted in devices such as cellular phones, and is likely to become popular in personal computers in the United States in the future. Initially, the BGA has a pin (bump) center-to-center distance of 1.5mm and a pin count of 225. There are also some LSI manufacturers that are developing 500-pin BGAs. The problem with BGA is the visual inspection after reflow soldering. It is not clear whether an effective visual inspection method is available. Some believe that because the center distance of the weld is large, the connection can be regarded as stable and can only be handled by functional inspection. Motorola of the United States refers to a package sealed with a molded resin as OMPAC, and a package sealed by a potting method is called GPAC.

2, BQFP package (quadflatpackagewithbumper)


Quad flat-lead package with pad. One of the QFP packages has protrusions (cushions) at the four corners of the package body to prevent bending deformation of the pins during shipping. US semiconductor manufacturers mainly use this package in circuits such as microprocessors and ASICs. The center of the pin is 0.635mm and the number of pins is from 84 to 196.


3, bump welding PGA package (buttjointpingridarray)


Another name for surface mount type PGA (see surface mount type PGA).


4, C- (ceramic) package


Indicates the mark of the ceramic package. For example, CDIP stands for ceramic DIP. It is a mark that is often used in practice.


5, Cerdip package


Glass-sealed ceramic dual in-line package for circuits such as ECLRAM, DSP (Digital Signal Processor). Cerdip with glass window is used for UV-erasing EPROM and internal microcomputer circuit with EPROM. The center of the pin is 2.54mm and the number of pins is from 8 to 42. In Japan, this package is denoted as DIP-G (G is the meaning of glass seal).


6, Cerquad package


One of the surface mount packages, that is, a ceramic QFP sealed with a lower seal, is used to package a logic LSI circuit such as a DSP. Cerquad with a window is used to encapsulate the EPROM circuit. The heat dissipation is better than that of plastic QFP, and it can tolerate 1.5 to 2W under natural air cooling conditions. But the packaging cost is 3 to 5 times higher than plastic QFP. The center distance of the pins is 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm and other specifications. The number of pins is from 32 to 368.

A ceramic chip carrier with a lead, one of the surface mount packages, with leads drawn from the four sides of the package in a T-shape. A window with a UV-erasing type EPROM and a microcomputer circuit with an EPROM. This package is also known as QFJ, QFJ-G (see QFJ).


7, CLCC package (ceramicleadedchipcarrier)


A ceramic chip carrier with a lead, one of the surface mount packages, with leads drawn from the four sides of the package in a T-shape. A window with a UV-erasing type EPROM and a microcomputer circuit with an EPROM. This package is also called QFJ, QFJ-G.


8, COB package (chiponboard)


The chip-on-board package is one of the bare chip mounting technologies. The semiconductor chip is placed on the printed circuit board. The electrical connection between the chip and the substrate is realized by the wire stitching method. The electrical connection between the chip and the substrate is realized by the wire stitching method. Resin coverage to ensure compatibility. Although COB is the simplest die-on-die technology, its packaging density is far less than that of TAB and flip chip bonding.


9, DFP (dualflatpackage)


Double-sided pin flat package. It is another name for SOP (see SOP). I used to have this method before, and now I have basically not used it.


10, DIC (dualin-lineceramicpackage)


Another name for ceramic DIP (including glass seal)